1 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 logic block diagram 1 oe 1 le 1 o 0 c d 1 d 0 to 7 other channels 2 oe 2 le 2 o 0 c d 2 d 0 to 7 other channels product features: ?v cc = 5v 10% ? balanced output drivers: 12 ma ? output impedance: 35 w (typical) ? typical v olp (output ground bounce) < 0.5v at v cc = 5v, t a = 25c ? bus hold retains last active bus state during tri-state ? hysteresis on all inputs ? packages available: C 48-pin 240 mil wide plastic tssop (a) C 48-pin 300 mil wide plastic ssop (v) C 48-pin 150 mil wide plastic bqsop (b) ? device models available on request product description: pericom semiconductors pi74fct series of logic circuits are pro- duced in the companys advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct162q373t is a 16-bit transparent latch designed with 3- state outputs and are intended for bus oriented applications. the output enable and latch enable controls are organized to operate as two 8-bit latches or one 16-bit latch. when latch enable (le) is high, the flip-flops appear transparent to the data. the data that meets the set-up time when le is low is latched. when oe is high, the bus output is in the high impedance state. the pi74fct162q373t is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this device features a typical output impedance of 35 w eliminating the need for external terminating resistors for most bus interface applications. this noise suppression benefit is designated by the letter "q" (for quiet) in the part number. the pi74fct162q373t has "bus hold" which retains the input's last state whenever the input goes to high-impedance preventing "floating" inputs and eliminating the need for pull-up/down resistors. pi74fct162q373t fast low noise cmos 16-bit transparent latches
pi74fct162q373t low noise 16-bit transparent latches 2 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product pin description pin name description xoe output enable inputs (active low) xle latch enable inputs (active high) xdx inputs (1) xox 3-state outputs gnd ground v cc power inputs (1) outputs (1) x d xx oe xle xox hlh h llh l xh x z truth table note: 1. h = high voltage level x = don't care l = low voltage level z = high impedance 1 2 3 4 5 6 7 8 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 32 31 30 29 28 27 26 25 1 oe 1 o 0 1 o 1 gnd 1 o 2 1 o 3 v cc 1 o 4 1 o 5 gnd 1 o 6 1 o 7 2 o 0 2 o 1 gnd 2 o 2 2 o 3 v cc 2 o 4 2 o 5 gnd 2 o 6 2 o 7 2 oe 48-pin v48 a48 b48 1 le 1 d 0 1 d 1 gnd 1 d 2 1 d 3 v cc 1 d 4 1 d 5 gnd 1 d 6 1 d 7 2 d 0 2 d 1 gnd 2 d 2 2 d 3 v cc 2 d 4 2 d 5 gnd 2 d 6 2 d 7 2 le product pin configuration note: 1. for the pi74fct162q373t, these pins have "bus hold". all other pins are standard, outputs, or i/os.
pi74fct162q373t low noise 16-bit transparent latches 3 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current standard input (4) , v cc = max. v in = v cc 1a i ih input high current bus hold input (5) , v cc = max. v in = v cc 100 a i il input low current standard input (4) , v cc = min. v in = gnd C1 a i il input low current bus hold input (5) , v cc = min. v in = gnd 100 a i bhh bus hold bus hold input (5) , v cc = min. v in = 2.0v C50 a i bhl sustain current v in = 0.8v +50 i ozh high impedance v cc = max. v out = 2.7v 1 a i ozl output current v cc = max. v out = 0.5v C1 a v ik clamp diode voltage v cc = min., i in = C18 ma C0.7 C1.2 v i o output drive current v cc = max. (3) , v out = 2.5v C50 C180 ma v h input hysteresis 100 mv maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .................................................................... C65c to +150c ambient temperature with power applied .................................... C40c to +85c supply voltage to ground potential (inputs & vcc only) .............. C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ........... C0.5v to +7.0v dc input voltage ............................................................................ C0.5v to +7.0v dc output current ..................................................................................... 120 ma power dissipation .......................................................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5 a at t a = C55c. 5. pins with bus hold are identified in the pin description. 6. this specification does not apply to bi-directional functionalities with bus hold.
pi74fct162q373t low noise 16-bit transparent latches 4 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 36 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) C100 C166 C200 ma output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C12.0 ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 12 ma 0.3 0.55 v notes: 1. for max. or min. condtions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf
pi74fct162q373t low noise 16-bit transparent latches 5 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 500 a supply current d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 1.5 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 60 100 a / input per mhz (4) outputs open v in = gnd mhz x oe = gnd, x le = v cc one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 0.6 1.5 (5) ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle x oe = gnd, x le = v cc one bit toggling v in = 3.4v 0.9 2.3 (5) v in = gnd v cc = max., v in = v cc 2.5 5.5 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle x oe = gnd, x le = v cc 16 bits toggling v in = 3.4v 6.4 16.5 (5) v in = gnd notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
pi74fct162q373t low noise 16-bit transparent latches 6 ps2081c 06/08/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t 3 7 3 q 2 6 1t a 3 7 3 q 2 6 1t c 3 7 3 q 2 6 1t d 3 7 3 q 2 6 1t e 3 7 3 q 2 6 1 t i n u . m o c. m o c. m o c. m o c. m o c n i mx a mn i mx a mn i mx a mn i mx a mn i mx a m t plh t phl y a l e d n o i t a g a p o r p x o x o t x d x c l =0 5 p f 1 r= 0 0 5 5 . 10 . 85 . 15 . 65 . 12 . 55 . 12 . 45 . 14 . 3 s n t plh t phl y a l e d n o i t a g a p o r p x o x o t e l x 0 . 20 . 3 10 . 25 . 80 . 25 . 55 . 10 . 45 . 17 . 3 t pzh t pzl e m i t e l b a n e t u p t u o x o x o t e o x 5 . 10 . 2 15 . 15 . 65 . 15 . 55 . 18 . 45 . 18 . 4 t phz t plz e m i t e l b a s i d t u p t u o ) 3 ( x o x o t e o x 5 . 15 . 75 . 15 . 55 . 10 . 55 . 10 . 45 . 10 . 4 t su e m i t e l b a s i d t u p t u o e l x o t x d x , w o l 0 . 2-0 . 2-0 . 2-5 . 1- 0 . 1- t h r o h g i h e m i t d l o h e l x o t x d x , w o l 5 . 1- 5 . 1-5 . 1- 0 . 1- 0 . 1- t w h t d i w e s l u p e l x h g i h ) 3 ( 0 . 6-0 . 5-0 . 5-0 . 3- 0 . 3- t sk ( o )w e k s t u o t u o ) 4 ( -5 . 0- 5 . 0-5 . 0-5 . 0-5 . 0 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com switching characteristics over operating range
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